The present invention relates to an insulated gate semiconductor device having a base-to-source electrode short and to a method of fabricating such short.
Insulated-gate semiconductor devices are devices employing a gate, or control electrode, insulatingly spaced from semiconductor material, for altering the conductivity of the semiconductor material beneath the gate. Typical insulated-gate devices include Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), which are well-known devices, and Insulated Gate Transistors (IGTs), (formerly designated "Insulated Gate Rectifiers") such as described in an article by B. J. Baliga et al., "The Insulated Gate Rectifier (IGR): A New Power Switching Device", IDEM (December 1982), pages 264-267. Both MOSFETs and IGTs are typically comprised of a multitude of repeated, individual "cells", with device current-carrying capability increasing as cell size is made smaller.
A base-to-source electrode short is typically employed in MOSFETs and IGTs and, most commonly, comprises a portion of the source electrode electrically shorting together a "P", or moderately-doped, P-conductivity type, base region and an "N+", or highly-doped, N-conductivity type, source region. This helps to ensure that the base-to-source P-N junction between the P base region and the N+ source region does not become forward biased (due to hole current in the P+ region, for example) to such an extent that the N+ source commences electron injection into the P base region, across the base-to-source P-N junction. Such electron injection is deleterious to both MOSFETs and IGTs. In an IGT, for example, such electron injection results in the device latching into an "on", or current-conducting state, as in a thyristor, with attendant loss of gate control over device current.
Even when using the foregoing base-to-source electrode short of the prior art, hole current in the P base region may still cause a voltage drop along the base-to-source P-N junction which is sufficient to result in undesired electron injection by the N+ source region. One prior art technique directed to minimizing the hole current voltage drop in the P base region, and thus the likelihood of undesired electron injection by the N+ source region, is to form, through the use of a specially aligned mask, a "P+", or highly-doped, P-conductivity type, shorting region in a selected portion of the P base region adjacent the base-to-source P-N junction. Hole current that flows in the P+ shorting region accordingly creates only a low voltage drop therein and is thus less likely to result in undesired electron injection by the N+ source region.
A drawback of the foregoing technique for minimizing the hole current voltage drop along the base-to-short P-N junction is in the requirement for a specially-aligned mask in forming the P+ shorting region. This significantly adds to fabrication expense and necessitates a larger cell size, resulting in a reduced current-carrying capability for the device.
Accordingly, it is an object of the present invention to provide an insulated-gate semiconductor device with a highly effective base-to-source electrode short.
A further object of the invention is to provide an insulated-gate semiconductor device having a base-to-source electrode short and having a reduced cell size compared to prior art devices.
Another object of the invention is to provide a semiconductor device having a base-to-source electrode short that can be fabricated with only a marginal increase in fabrication complexity and cost.
A still further object of the invention is to provide a method of fabricating an improved shorting region in a semiconductor device having a base-to-source electrode short.
In accordance with a preferred form of the invention, there is provided a semiconductor device with an improved base-to-source electrode short. The device comprises a semiconductor wafer having a substantially-planar upper surface and including: an N voltage-supporting layer; a P base region overlying the N voltage-supporting layer and having a portion terminating in proximity to the wafer upper surface; and an N+ source region overlying the P base region. The semiconductor device includes a gate above the wafer and insulatingly spaced therefrom and a source electrode situated above the wafer and conductively coupled to the N+ source region. A P+ implant shorting region is included in the wafer with at least the major portion of the upper surface thereof being situated beneath the plane of the wafer upper surface source and P base regions. The implant shorting region adjoins the N+ source and base regions, has a higher conductivity than the P base region and is conductively coupled to the source electrode so as to complete the short between the P base region and the source electrode.
In accordance with a further, preferred form of the invention, there is provided a method of fabricating an implant shorting region in an insulated-gate semiconductor device. The method includes the step of providing a semiconductor wafer having a substantially-planar upper surface and including, in successively adjoining relationship, an N+ source region, a P base region, and an N voltage-supporting layer. A gate insulatingly spaced from the wafer is formed atop the wafer. The gate is utilized as an integral part of an implant mask while implanting into the wafer a P+ implant shorting region at a sufficiently high energy level that the P+ implant shorting region is located, at least in major part, beneath the wafer upper surface and adjoining both the N+ source and P base regions. A source electrode is conductively connected to the N+ source region and the P+ implant shorting region.